Low Power Dissipation MOS Ternary Logic Family

An MOS ternary-logic family is proposed, which is comprised of a set of inverters, NOR gates, and NAND gates. These gates are used to design basic ternary arithmetic and memory circuits. The circuits thus obtained are then used to synthesize complex ternary arithmetic circuits and shift registers. The ternary circuits developed are shown to have some significant advantages relative to other known ternary circuits like low power dissipation, and reduced propagation delay and component count. For a given dynamic range, the complexity of the new ternary circuits is shown to be comparable to that of corresponding binary circuits. Nevertheless, the associated reduction in the wordlength in the case of the ternary circuits tends to alleviate to a large extent the pin limitation problem associated with VLSI implementation. The paper concludes with an implementation of the cyclic convolution, an application in which a significant advantage can be gained through the use of ternary digital hardware. T HREE-VALUED, or ternary, logic offers several important advantages over binary logic in the design of digital systems [I], [2]. For example, more information can be transmitted over a given set of lines or stored for a given register length, the complexity of interconnections can be reduced, reduction in chip area can be achieved, and more efficient error-detection and error-correction codes can be employed. Furthermore, serial and some serial-parallel arithmetic operations can be carried out at higher speeds. Most of these advantages have a direct bearing on the VLSI implementation of digital systems, and as a result several realizations of basic ternary gates have been proposed in the literature [2]-[7]. These have been shown to be useful for the design of "ternary computers," for digital filtering [8], and for various other applications [I]-[9]. Higucb and Kameyama have shown that the realization of combinational and sequential logic functions is possible using a ternary logic element which they refer to as the T-gate [4]. In addition, they have proposed an implementation of the T-gate using bipolar transistors, and considered its application to the synthesis of combinational as well as sequential logic circuits [5]. Recently, Mouftah and Smith have proposed an alternative implementation of the T-gate using MOS technology [lo], [Ill. The synthesis of an N-variable combinational logic circuit requires ( 3 N 1)/2 Manuscript received November 1, 1983; revibed April 12, 1984. This work was supported by the Natural Sciences and Engineering Rcsearch Council of Canada. The authors are with the Department of Electrical Engineering, University of Victoria, Victoria, BC, Canada V8W 2Y2. T-gates, as was demonstrated in [4] and [5] and, consequently, the complexity of the logic circuit increases rapidly as the number of variables is increased. This appears to be a major limitation of ternary logic design based on the T-gate. In this contribution, an alternative ternary logic family is proposed, which can be used in the design of combmational and sequential ternary logic circuits. The new farnily is based on MOS technology and is thus amenable to V LSI implementation. It is comprised of a set of inverters, NOR gates, and NAND gates. These circuits are used to design ternary memory elements and some basic ternary arithmetic circuits like half and full adders, and the one-ltritl multiplier. The circuits thus obtained are then used to synthesize a shift register, an N-trit adder, and an N-4rit multiplier. The proposed circuits are shown to have some significant advantages relative to other ternary circuits based on the T-gate like low power dissipation, reduced propaga1.ion delay, and also reduced component count. In order to demonstrate the usefulness of the proposed , ternary circuits, the implementation of cyclic convolution is considered. As is demonstrated in [12], this is an app'lication where a significant advantage can be gained by using ternary digital hardware, namely, an increased maxinl~um sequence length can be achieved without increasing the complexity of the digital hardware. The most fundamental building blocks in the design of digital systems are the inverter, NOR gate, and NAND &ate. In this section, new ternary implementations are propo'sed for the inverter, NOR gate, and NAND gate, in which the static power dissipation is low. The logic symbolism assumed is shown in Table I. A. General Ternary Inverter A general ternary inverter (GTI) is a device with one input x. and three outputs yo, y,, and y, such that 'A tnt is a ternary digit. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-19, NO. 5 , OCTOBER 1984 TABLE I LOGIC SYMBOLISM